Design techniques to reduce SET pulse widths in deep-submicron combinational logic

被引：79

作者：

Amusan, Oluwole A. ^{[1
]}

Massengill, Lloyd W. ^{[1
]}

Bhuva, Bharat L. ^{[1
]}

DasGupta, Sandeepan ^{[1
]}

Witulski, Arthur F. ^{[2
]}

Ahlbin, Jonathan R. ^{[1
]}

机构：

[1] Vanderbilt Univ, Dept Elect Engn & Comp Sci, Nashville, TN 37235 USA

[2] Vanderbilt Univ, Inst Space & Def Elect, Nashville, TN 37235 USA

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2007年 / 54卷 / 06期

关键词：

charge collection; charge confinement; lateral parasitic bipolar; n-well collapse; n-well contact area; n-well contact location; radiation hardened by design; transistor sizing;

D O I：

10.1109/TNS.2007.907754

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

引用

页码：2060 / 2064

页数：5

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