High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay

被引：0
作者：
Li, Xiangwei [1 ]
Vipin, Kizheppatt [2 ]
Maskell, Douglas L. [3 ]
Fahmy, Suhaib A. [4 ]
Jain, Abhishek Kumar [5 ]
机构：
[1] Univ Sydney, Sch Elect & Informat Engn, Sydney, NSW, Australia
[2] Nazarbayev Univ, Sch Engn & Digital Sci, Nur Sultan, Kazakhstan
[3] Nanyang Technol Univ, Sch Comp Sci & Engn, Singapore, Singapore
[4] Univ Warwick, Sch Engn, Warwick, England
[5] Xilinx Inc, San Jose, CA USA
来源：
2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2020年
关键词：
D O I：
10.1109/iscas45731.2020.9181072
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically processor-based computing system, an aspect which has often been neglected in evaluations of overlays. We explore the integration of a time-multiplexed FPGA overlay over a server-class PCI Express interface. We show how this integration can be optimised to maximise performance, and evaluate the area overhead. We also propose a user-friendly programming model for such an overlay accelerator system.
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收藏
页数：5
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