Synchronous elastic circuits with early evaluation and token counterflow

被引：26
|
作者：
Cortadella, Jordi [1 ]
Kishinevsky, Mike [2 ]
机构：
[1] Univ Politecn Cataluna, Barcelona, Spain
[2] Intel Corp, Strateg CAD Lab, Hillsboro, OR USA
来源：
2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2007年
关键词：
elastic designs; protocols; synthesis;
D O I：
10.1109/DAC.2007.375199
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in the forward direction and anti-tokens canceling information move in the backward direction. An implementation of the protocol and an example illustrate the flow for converting a regular synchronous design into an elastic circuit with early evaluation.
引用
收藏
页码：416 / +
页数：2
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