A Low-Power, 9-Bit, 1.2 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS

被引：0

作者：

Hamza, A. ^{[1
]}

Ibrahim, S. ^{[1
]}

El-Nozahi, M. ^{[1
]}

Dessouky, M. ^{[1
]}

机构：

[1] Ain Shams Univ, Integrated Circuits Lab, Elect & Commun Engn Dept, Fac Engn, Cairo, Egypt

来源：

2015 IEEE 13TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS) | 2015年

关键词：

Time-to-digital converter (TDC); time amplifier (TA); all-digital phase-locked loop (ADPLL); BIT;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of a low-power, 9-bit, two-step time-to-digital converter (TDC) in 65 nm CMOS. Instead of using an array of time amplifiers (TAs) to amplify the time residue, the proposed TDC reduces the power and area consumptions by using only one TA. The designed TDC achieves a resolution of 1.2 ps with a conversion range of 0.614 ns while consuming 0.602 mW at 10 MHz and 8.299 mW at 150 MHz. The achieved figure-of-merit (FoM) of the TDC is 0.108 pJ/conversion at a frequency of 150 MHz.

引用

页数：4

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