Solder bump reliability - Issues on bump layout

被引：11

作者：

Alander, T ^{[1
]}

Heino, P ^{[1
]}

Ristolainen, E ^{[1
]}

机构：

[1] Tampere Univ Technol, Inst Elect, FIN-33101 Tampere, Finland

来源：

IEEE TRANSACTIONS ON ADVANCED PACKAGING | 2000年 / 23卷 / 04期

关键词：

bump layout; FEM; flip chip; reliability; solder bump;

D O I：

10.1109/6040.883763

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The reliability of solder bumps in a typical under-filled flip chip package is calculated three-dimensionally (3-D) using the finite element method and a viscoplastic material model for the solder, Simulations are performed with varying bump placement, underfill coverage, and board size, The average plastic work in a bump is used to compare the loading and bump reliability of different geometries. The results show possible improvements over the traditional bump placement by changing the geometry of the interconnects on the flip chip package, Three changes that improve reliability are discussed in detail: the redistribution of bump rows, the reduction of board size, and the inclusion of heat transfer bumps.

引用

页码：715 / 720

页数：6

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