7Gbit/s measurements on a 0.8μm CMOS line-receiver

Successful sampling of every 32nd bit in a 7-Gbit/s data stream has been shown with a 0.8-mu m CMOS circuit which is based on parallel sampling. The input bandwidth of the chip is the suspected bit rate limiting factor. The input bandwidth is mainly set by the wire characteristic impedance and the input capacitance of the chip. Half of a 5-Gbit/s data stream has been received by the same circuit. This indicates that (full) reception of 5-Gbit/s data-streams is possible. The bit rate limiting factor in this case is the accuracy and jitter of the control-clocks to the sampling-switches.