Optimization of DUV lithography for high-energy well implantation

Presented here is an analysis of photoresist profile and feature control performance for high-energy well implant lithography as it is implemented in microelectronic devices, specifically SRAMs, at the 45 and 65nm nodes. As device designs become increasingly smaller to the tune of Moore's Law, deep well implant lithography specifications become more and more stringent, and issues related to lateral implant scattering that were more trivial for more relaxed designs begin to make significant contributions to photoresist feature uniformity and implant profile control. Simplified process assumptions that overlook such non-ideal implant phenomena can result in an overestimation of process latitude. Undesirable variability derived from the implantation, lithography, and substrate associated with a deep well formation process can degrade implantation profiles and have adverse effects on device electrical performance. Mechanisms for these adverse effects such as implant scattering and implant straggle will be explored followed by their relationships to process tolerance and electrical performance. Emphasis will be placed on evaluating the optimum photoresist feature profile for a given process and determining its true process latitude as opposed to "centering" a feature in a device layout during design. Finally, challenges confronting process control methods for high-aspect ratio implant mask features will be discussed followed by some proposed process improvement suggestions.