Strain enhanced FUSI/HfSiON technology with optimized CMOS process window

被引:1
作者
Veloso, A. [1 ]
Verheyen, P. [1 ]
Vos, R. [1 ]
Brus, S. [1 ]
Ito, S. [2 ]
Mitsuhashi, R. [2 ]
Paraschiv, V. [1 ]
Shi, X. [1 ]
Onsia, B. [1 ]
Arnauts, S. [1 ]
Loo, R. [1 ]
Lauwers, A. [1 ]
Conard, T. [1 ]
de Marneffe, J. -F. [1 ]
Goossens, D. [1 ]
Baute, D. [1 ]
Locorotondo, S. [1 ]
Chiarella, T. [1 ]
Kerner, C. [1 ]
Vrancken, C. [1 ]
Mertens, S. [1 ]
O'Sullivan, B. J. [1 ]
Yu, H. Y. [1 ]
Chang, S. -Z. [3 ,4 ]
Niwa, M. [2 ]
Kitt, J. A. [4 ]
Absil, P. P. [1 ]
Jurczak, M. [1 ]
Hoffmann, T. [1 ]
Biesemans, S. [1 ]
机构
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
[2] Matsushita, B-3001 Leuven, Belgium
[3] TSMC, B-3001 Leuven, Belgium
[4] Texas Instruments Inc, B-3001 Leuven, Belgium
来源
2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2007年
关键词
D O I
10.1109/VLSIT.2007.4339692
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report, for the first time, a comprehensive study on the compatibility of state-of-the-art performance boosters with FUSI/HfSiON technology, resulting in record high-V-T NMOS and PMOS devices with 725/370 mu A/mu m (at V-DD=1.1 V, Ioff=20pA/mu m and Jg=100/1 mA/cm(2)). We demonstrate that adding embedded Si0.75Ge0.25 in S/D regions resulted in 45% performance improvement over the FUSI/HfSiON reference, and that the V-T distribution is tight and comparable to baseline. For process simplicity purposes, dual phase Ni-FUSI (NiSi NMOS; Ni31Si12 or Ni2Si PMOS) is formed simultaneously in our integration scheme, each phase having its own process window (PW). In this work, we successfully maximized the common CMOS PW by 2 crucial process improvements: - shifting up the NMOS RTP1 temperature (T) PW by nitrogen implantation in NMOS poly gates prior to Ni deposition for FUSE - extending the PMOS PW to lower RTP1 temperatures by improved surface preparation after novel poly etch-back process.
引用
收藏
页码:200 / +
页数:2
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