A Low Power Fully-Integrated 76-81 GHz ADPLL for Automotive Radar Applications with 150 MHz/us FMCW Chirp Rate and-95dBc/Hz Phase Noise at 1 MHz Offset in FDSOI

被引：0

作者：

Fridi, Ahmed R. ^{[1
]}

Zhang, Chi ^{[1
]}

Bellaouar, Abdellatif ^{[1
]}

Tran, Man ^{[2
]}

机构：

[1] GLOBALFOUNDRIES, RF & MmWave Design Team, Dallas, TX 75243 USA

[2] Mantr Technol, Toronto, ON, Canada

来源：

2019 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC) | 2019年

关键词：

Digital PLL; FMCW; radar; mmWave; 79; GHz;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a fully integrated 76-81 GHz All Digital PLL for FMCW automotive radar applications is presented. It features a 20 GHz digital PLL followed by a 4x multiplier and buffer. The proposed ADPLL is implemented in a 22nm fully depleted SOI CMOS technology. It achieves up to 150 MHz/us FMCW chirp rate over a 4 GHz bandwidth and dissipates 85mW only.

引用

页码：327 / 330

页数：4