Scaling of parasitics and delay times in the backend-of-line

The role of interconnects in determining the delay times of future generation integrated circuits has been studied. Two scenarios were investigated; one using ITRS values for dielectric permeability and conductor resistivity, and an alternative taking into account size effects on the resistivity and using more conservative values for k. To develop a concise model of the delays, the contributions of the individual parasitic elements and their evolution for future generations were investigated for the different scenarios. The calculations of the delays show a dramatic increase for small feature sizes. The predictions of the two models differ significantly especially for long wires, with the conservative model showing much longer delay times. These results make the introduction of a hierarchical metallization seem even more important. (C) 2003 Elsevier B.V. All rights reserved.