System-level performance estimation strategy for Sw and Hw

被引：4

作者：

Allara, A ^{[1
]}

Brandolese, C ^{[1
]}

Fornaciari, W ^{[1
]}

Salice, F ^{[1
]}

Sciuto, D ^{[1
]}

机构：

[1] ITALTEL, Cent Res Labs, CLTE, I-20019 Castelletto Di Settimo, MI, Italy

来源：

INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/ICCD.1998.727022

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The design of an embedded system is a process where the timing of the architecture should rake into account both the functionality and the timing performance while considering the heterogeneity of the hw and sw components. The goal of this paper is to present the new model developed during the SEED Esprit project, to estimate the software and hardware characteristics for cosimulation and profiling within the TOSCA codesign framework. The impact on the design space exploration of such an high-level cosimulation strategy has been tested by considering as a benchmark the reengineering of an industrial device.

引用

页码：48 / 53

页数：6