Nanodot and nanowire transistor device Modeling and fabrication process

被引：8

作者：

Chen, Yijian ^{[1
]}

机构：

[1] Appl Mat Inc, Santa Clara, CA 95054 USA

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS | 2007年 / 46卷 / 9B期

关键词：

nanodot; nanowire; MOSFET; surrounding gate; Poisson's equation;

D O I：

10.1143/JJAP.46.6213

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

In this paper, we propose nanodot- and nanowire-based metal-oxide-semiconductor field effect transistors (MOSFETs) that can be fabricated by a process that does not require extremely high lithographic resolution. The MOSFET devices remain functional even when nanodots and nanowires of various sizes are randomly distributed. The device physics and modeling of nanodot and nanowire MOSFETs are presented. The (analytical) general solution to Poisson's equation for nanowire MOSFET is given. Moreover, we apply a boundary-condition coupled transformation technique to linearize the original Poisson's equation for nanodot MOSFET to such a form that an analytical solution can be obtained. It is shown that this analytical solution is an accurate description of the electric potential and inversion charge concentration in nanodot MOSFET. The stochastic characteristics of the device parameters of nanodot and nanowire MOSFETs are studied and several important process control issues are discussed. The approximate formulas for calculating the total inversion charge in the ultrathin bodies of nanodot and nanowire MOSFETs are presented.

引用

页码：6213 / 6217

页数：5

共 6 条

[1]

Chen Y., 2001, P INT C MOD SIM MICR, P546

[2] Vertical integrated-gate CMOS for ultra-dense IC [J].

Chen, YJ ;

Chu, A .

MICROELECTRONIC ENGINEERING, 2006, 83 (4-9) :1745-1748

[3] Oxidation of Si nanocrystals fabricated by ultralow-energy ion implantation in thin SiO2 layers [J].

Coffin, H ;

Bonafos, C ;

Schamm, S ;

Cherkashin, N ;

Assayag, GB ;

Claverie, A ;

Respaud, M ;

Dimitrakis, P ;

Normand, P .

JOURNAL OF APPLIED PHYSICS, 2006, 99 (04)

[4] High performance silicon nanowire field effect transistors [J].

Cui, Y ;

Zhong, ZH ;

Wang, DL ;

Wang, WU ;

Lieber, CM .

NANO LETTERS, 2003, 3 (02) :149-152

[5] Continuous analytic I-V model for surrounding-gate MOSFETs [J].

Jiménez, D ;

Iñíguez, B ;

Suñé, J ;

Marsal, LF ;

Pallarès, J ;

Roig, J ;

Flores, D .

IEEE ELECTRON DEVICE LETTERS, 2004, 25 (08) :571-573

[6] High-performance fully depleted silicon-nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices [J].

Singh, N. ;

Agarwal, A. ;

Bera, L. K. ;

Liow, T. Y. ;

Yang, R. ;

Rustagi, S. C. ;

Tung, C. H. ;

Kumar, R. ;

Lo, G. Q. ;

Balasubramanian, N. ;

Kwong, D. -L. .

IEEE ELECTRON DEVICE LETTERS, 2006, 27 (05) :383-386

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