CMOS RF Low-Noise Amplifier Design for Variability and Reliability

被引:17
作者
Liu, Yidong [1 ]
Yuan, Jiann-Shiun [1 ]
机构
[1] Univ Cent Florida, Sch Elect Engn & Comp Sci, Orlando, FL 32816 USA
关键词
Adaptive body bias; design for reliability (DFR); low-noise amplifier (LNA); Monte Carlo simulation; noise figure; radio frequency (RF); small-signal model; variability; BREAKDOWN; DEVICE;
D O I
10.1109/TDMR.2011.2160350
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An adaptive substrate (body) bias design for variability and reliability for a CMOS low-noise amplifier (LNA) is analyzed. The proposed body biasing scheme provides a radio-frequency circuit that is resilient to process variations and device reliability. Small-signal models including substrate bias effect are developed for noise figure and small-signal power gain sensitivity. The cascode LNA operating at 24 GHz with the adaptive substrate bias scheme is compared with the LNA without body bias using the PTM 65-nm technology. The modeling and simulation results show that the adaptive substrate bias reduces the sensitivity of noise figure and minimum noise figure subject to process variations and device aging such as threshold voltage shift and electron mobility degradation.
引用
收藏
页码:450 / 457
页数:8
相关论文
共 25 条
[1]   Penelope :: The NBTI-Aware processor [J].
Abella, Jaume ;
Vera, Xavier ;
Gonzalez, Antonio .
MICRO-40: PROCEEDINGS OF THE 40TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, 2007, :85-+
[2]  
Abrishami Hamed., 2008, GLSVLSI 08, P29
[3]   Ring oscillators for CMOS process tuning and variability control [J].
Bhushan, M ;
Gattiker, A ;
Ketchen, MB ;
Das, KK .
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 2006, 19 (01) :10-18
[4]   Extremely scaled silicon nano-CMOS devices [J].
Chang, LL ;
Choi, YK ;
Ha, DW ;
Ranade, P ;
Xiong, SY ;
Bokor, J ;
Hu, CM ;
King, TJ .
PROCEEDINGS OF THE IEEE, 2003, 91 (11) :1860-1873
[5]   A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration [J].
Chen, Tao ;
Gielen, Georges G. E. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (11) :2386-2394
[6]  
Chen Z, 2000, MICROW OPT TECHN LET, V26, P1, DOI 10.1002/(SICI)1098-2760(20000705)26:1<1::AID-MOP1>3.0.CO
[7]  
2-E
[8]   Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide [J].
Denais, M ;
Huard, V ;
Parthasarathy, C ;
Ribes, G ;
Perrier, F ;
Revil, N ;
Bravaix, A .
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (04) :715-722
[9]   Soft breakdown of ultra-thin gate oxide layers [J].
Depas, M ;
Nigam, T ;
Heyns, MM .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (09) :1499-1504
[10]  
Dierickx B, 2007, SCALING BELOW 90 NM