Pathfinder Based on Simulated Annealing for Solving Placement and Routing Problem

被引：0

作者：

Yu, Zhangyi ^{[1
]}

Zeng, Sanyou ^{[1
]}

Guo, Yan ^{[1
]}

Hu, Nannan ^{[1
]}

Song, Liguo ^{[2
]}

机构：

[1] China Univ Geosci, Sch Comp Sci, Wuhan 430074, Peoples R China

[2] Microelect Technol Inst Beijing, Beijing 100076, Peoples R China

来源：

ADVANCES IN COMPUTATION AND INTELLIGENCE | 2010年 / 6382卷

基金：

中国国家自然科学基金;

关键词：

Evolvable hardware; Obstacle avoidance; simulated annealing; Pathfinder; Placement and routing;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The placement and routing is a hot topic in Evolvable Hardware, the work of the placement and routing in this paper is as follows: (1) Combining with FPGA's and the VPR's "placement and routing" two-stage optimization model, the designed "random placement and optimal routing" model meets the tasks of placement and routing in PEA that is N*N array of PE. (2)The designed pathfinder based on simulated annealing is a solution for the "placement and optimal routing" cycle model, it uses obstacle avoidance to solve the placement and routing problem. (3)By numerical test experiments, we verify that the success rate of pathfinder based on simulated annealing is higher than the commonly used "depth-first search" under the PEA framework.

引用

页码：390 / +

页数：2