Low-Loss Ka-band SPDT Switch Design Methodology for 5G Applications in 65 nm CMOS SOI Technology

This paper presents a design methodology for front end module SPDT switches. Then it is applied to an advanced CMOS SOI circuit for Ka-band 5G mobile communications. Firstly the specifications are discussed to address the targeted use case. The chosen technology, offering a simulated FoM of 110 fs, is introduced. Then, the easily scalable non technology dependent design methodology is presented. Measurement results of a series-shunt switch demonstrator are reported for methodology validation. The fabricated SPDT achieves insertion losses lower than 1 dB and an isolation above 20 dB in the 24-31 GHz frequency range. The measured performances are comparable to other recently reported SPDT based on advanced CMOS technologies.