Gate oxide breakdown characterization on 0.13μm CMOS technology

With the continuously shrinking device dimensions, it becomes more difficult to found the defects on the semi-conductor products for the failure analysis (FA). The gate oxides breakdown are especially difficult to locate and inspect on the integrated circuits (IC). In this paper, we report three cases studies (0.13 mum CMOS technology) analysed by Sub-Micron Probing Technique (SMP) in the Nice Device Analysis Laboratory (NDAL) of Texas-Instruments France in order to show our own way to identify the gate oxide breakdown failure mechanism with the appropriate delayering technique. The complementary TEM cross-section analysis of the third case will permit to make assumptions about the root cause of this failure mechanism. (C) 2003 Elsevier Ltd. All rights reserved.