Physics-based analytic modeling and simulation of gate-induced drain leakage and linearity assessment in dual-metal junctionless accumulation nano-tube FET (DM-JAM-TFET)

Physics-based analytical model is proposed in this paper which analyzes the effect of temperature, channel length and silicon film radius on gate-induced drain leakages (GIDL) in dual-metal junctionless accumulation nano-tube FET (DM-JAM-TFET). Formulation and analysis for electric field, E-z, surface potential and gate-induced drain leakage current, I-gidl have been done with the help of appropriate boundary conditions utilized in solving two-dimensional Poisson's equation. Also, the effect of variation in temperatures at T = 300 K and 500 K, silicon film channel length (L 30 nm and 40 nm) and radius of R = 9 nm and R = 10 nm have been studied. The simulated results seem to be in good compliance with the analytical results. To analyze the applicability of DM-JAM-TFET for RFIC applications, linearity of the aforesaid device has been deeply investigated by comparing DM-JAM-TFET with JAM-GAA and DM-JAM-GAA at channel length, L = 20 nm. The linearity metrics namely g(m1), g(m2), g(m3), VIP2, VIP3, IMD3 and IIP3 have been significantly improved in DM-JAM-TFET making it intermodulation distortion resistant.