Characterization of border trap generation in rapid thermally annealed oxides deposited using silane chemistry

The border trap generation under high held stressing has been characterized in rapid thermal annealed low pressure chemical vapor deposited gate oxides. The hysteresis in high frequency capacitance-voltage curve is used to characterize the border traps. It is shown that at least some of the border traps are not associated with trapped positive charge. The border traps are charged and discharged through electrons tunneling from and to the substrate. The hysteresis is independent of temperature confirming the tunneling model. The effects of different annealing ambients suggest that the border trap generation depends on the physical stress at the substrate interface, which is qualitatively measured using Fourier transform infrared spectroscopy. The border trap generation is attributed to bond breaking at the substrate interface by energetic electrons. (C) 1998 American Institute of Physics. [S0021-8979(98)03217-4].