A low phase noise integrated SiGe 18..20 GHz fractional-N synthesizer

被引：0

作者：

Follmann, R. ^{[1
]}

Koether, D. ^{[1
]}

Kohl, T. ^{[1
]}

Engels, M. ^{[1
]}

Heyer, V. ^{[2
]}

Schmalz, K. ^{[3
]}

Herzel, F. ^{[3
]}

Winkler, W. ^{[3
]}

Osmany, S. ^{[3
]}

Jagdhold, U. ^{[3
]}

机构：

[1] IMST GmbH, D-47475 Kamp Lintfort, Germany

[2] Kayser Threde, D-81379 Munich, Germany

[3] IHP, D-15236 Frankfurt, Germany

来源：

2007 EUROPEAN CONFERENCE ON WIRELESS TECHNOLOGIES | 2007年

关键词：

VCO; PLL; synthesizer; SiGe; mixed signal; CMOS; satellite applications; downconverter;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The communication market demands broadband transmission, high density television (HDTV) and interactivity, whereby HDTV will become the leading application. All applications require a high number of individual channels, leading to a large number of up- and down-converters. These high needs can be served best with highly integrated SiGe MMICs. It has been demonstrated that the best suited RF-element to be developed is the Local Oscillator (LO) synthesizer, which fits well to the SiGe technology. The most critical building blocks of the LO are the voltage controlled oscillator (VCO) which is challenging in its phase noise behavior and the fractional-N divider with its large influence on phase noise and spurs. This paper will describe the flexible design of a MMIC, which can be used also as a PLL circuit together with an external oscillator in a broad frequency range.

引用

页码：1 / +

页数：2

共 5 条

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