Reliability of Chip-Last Fan-Out Panel-Level Packaging for Heterogeneous Integration

被引:2
作者
Lau, John H. [1 ]
Ko, Cheng-Ta [1 ]
Peng, Chia-Yu [1 ]
Yang, Kai-Ming [1 ]
Xia, Tim [1 ]
Lin, Puru Bruce [1 ]
Chen, Jean-Jou [1 ]
Huang, Po-Chun [1 ]
Tseng, Tzvy-Jang [1 ]
Lin, Eagle [1 ]
Chang, Leo [1 ]
Lin, Curry [1 ]
Fan, Yan-Jun [1 ]
Liu, Hsing-Ning [1 ]
Lu, Winnie [1 ]
机构
[1] Unimicron, Taoyuan, Taiwan
来源
IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021) | 2021年
关键词
D O I
10.1109/ECTC32696.2021.00067
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this study, the reliability of the solder joints of a heterogeneous integration of one large chip and two smaller chips by a fan-out method with a redistribution-layer (RDL)first substrate fabricated on a panel is investigated. Emphasis is placed on the thermal cycling test (-55 degrees C reversible arrow 125 degrees C, 50-minute cycle) of the heterogeneous integration package on a PCB (printed circuit board). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank arc presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A non-linear, time and temperature dependent 3D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.
引用
收藏
页码:359 / 364
页数:6
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