Batch-Normalized Deep Recurrent Neural Network for High-Speed Nonlinear Circuit Macromodeling

被引:25
作者
Faraji, Amin [1 ]
Noohi, Mostafa [2 ]
Sadrossadat, Sayed Alireza [1 ]
Mirvakili, Ali [2 ]
Na, Weicong [3 ]
Feng, Feng [4 ]
机构
[1] Yazd Univ, Dept Comp Engn, Yazd 8915818411, Iran
[2] Yazd Univ, Dept Elect Engn, Yazd 8915818411, Iran
[3] Beijing Univ Technol, Fac Informat Technol, Beijing 100124, Peoples R China
[4] Tianjin Univ, Sch Microelect, Tianjin 300072, Peoples R China
基金
中国国家自然科学基金;
关键词
Integrated circuit modeling; Training; Solid modeling; Neural networks; Behavioral sciences; Nonlinear circuits; Recurrent neural networks; Batch normalization (BN); computer-aided design (CAD); modeling; nonlinear circuits; recurrent neural network (RNN);
D O I
10.1109/TMTT.2022.3200071
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In order to model high-speed nonlinear circuits, recurrent neural network (RNN) has been widely used in computer-aided design (CAD) area to achieve high performance and fast models compared with the existing models. Despite their advantages, they still have challenges such as large training time and limited test accuracy. In this article, the batch normalization (BN) method is applied to deep RNN leading to a much shorter training time and more accurate models compared with the conventional RNN. The proposed BN-RNN method works by modifying the distribution of the internal nodes of a deep network in the training course as an internal auxiliary shift yielding a much faster training. Indeed, the internal covariance shift will be reduced and the training of deep neural networks will be accelerated via a normalization step applied to the layers of RNN. BN-RNN, moreover, has a beneficial effect on gradient flow through the grid by reducing the dependence of gradients on the scale of network parameters or their initial values. This provides a much better learning process without the risk of divergence. For verifying the proposed method, time-domain modeling of three high-speed nonlinear circuits operating at the GHz region is provided. Comparisons of the training and test errors between RNN and BN-RNN, and evaluation time comparisons between transistor level and the BN-RNN-based models for these circuits prove the higher speed of the models obtained from the BN-RNN method. In addition, it is shown that training using the proposed method requires much less CPU time and number of epochs.
引用
收藏
页码:4857 / 4868
页数:12
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