Management of common-mode currents in semiconductor ATE

Achieving the cost benefit of system integration without penalizing instrument performance requires careful attention to integration details. Instrument power management functions produce currents that are identified as a limit to the test system's noise floor. Dc-dc converter data and a SPICE analysis of common test system architecture justify a more complete methodology for qualifying instrument performance and a system standard is proposed. Measurements from a physical mockup validate the modeling. Common-mode current modeling and simulation can be used in instrumentation development to anticipate performance prior to laboratory validation.