As the design complexity grows dramatically in modem circuit designs, 2.5D/3D chip/package/board integration has become effective for optimizing system performance and power consumption. Various 2.5D/3D technologies have been explored. Among many technologies, wafer-level chip-scale packages have been adopted by major companies such as TSMC to achieve high-density, high-performance, low-cost packaging solutions. A simple combination of traditional tools is insufficient to achieve the desired design quality for chip-package-board integration of a heterogeneous system, which might lead to suboptimal solutions. Hence, in this work, we study the chip, package, and board codesign methodology with advanced packages and explore key techniques to handle the emerging challenges in physical design, timing, electrical effects, and testing. There are still many opportunities for future research to advance 2.5D/3D heterogeneous SoC integration.
