Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing

Distributed arithmetic (DA) is popularly adopted in many digital signal processing (DSP) applications, such as filtering, linear transformations and convolutions, with both area and energy benefits. DA utilizes Look-Up Tables (LUTs) that are implemented with SRAM to store all possible precomputed results. However, a direct implementation will lead to exponential LUT size increase with respect to the vector size. In this paper, we propose a novel in-memory computation design methodology to reduce the size of LUT without degrading the speed and power performance heavily. First, we propose a heuristic decomposition scheme that only leads to a minimal subset of the precomputed results to be stored in LUT. Second, we design a novel multi-bit in-memory adder exploiting charge-sharing based carry propagation. In the design case, when applying our method to the state-of-the-art DA-based FIR, the overall area is reduced by 10% while maintaining same speed and a similar level of energy.