Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25μm CMOS technology for embedded applications

被引：8

作者：

Bhat, N ^{[1
]}

Chen, P ^{[1
]}

Tsui, P ^{[1
]}

Das, A ^{[1
]}

Foisy, M ^{[1
]}

Shiho, Y ^{[1
]}

Higman, J ^{[1
]}

Nguyen, JY ^{[1
]}

Gonzales, S ^{[1
]}

Collins, S ^{[1
]}

Workman, D ^{[1
]}

机构：

[1] Motorola Inc, Networking & Comp Syst Grp, Austin, TX 78721 USA

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746507

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The competing effects of the well (super steep versus uniform channel) and the source/drain (LDD) structures are analyzed on the hot carrier degradation of 90 Angstrom, 3.3V I/O transistor integrated on a 0.25 mu m, 1.8V technology with a high performance 35 Angstrom, 1.8V core transistor. The cost vs. reliability trade offs in the dual gate oxide integration are discussed.

引用

页码：931 / 934

页数：4

共 2 条

[1]

TSUI P, 1998, VLSI TECH, P152

[2] A high performance 1.8V, 0.20μm CMOS technology with copper metallization [J].

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Gelatos, AV ;

Misra, V ;

Smith, B ;

Islam, R ;

Cope, J ;

Wilson, B ;

Tuttle, D ;

Cardwell, R ;

Anderson, S ;

Angyal, M ;

Bajaj, R ;

Capasso, C ;

Crabtree, P ;

Das, S ;

Farkas, J ;

Filipiak, S ;

Fiordalice, B ;

Freeman, M ;

Gilbert, PV ;

Herrick, M ;

Jain, A ;

Kawasaki, H ;

King, C ;

Klein, J ;

Lii, T ;

Reid, K ;

Saaranen, T ;

Simpson, C ;

Sparks, T ;

Tsui, P ;

Venkatraman, R ;

Watts, D ;

Weitzman, EJ ;

Woodruff, R ;

Yang, I ;

Bhat, N ;

Hamilton, G ;

Yu, Y .

INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :769-772

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