共 50 条
- [31] INTERFACIAL DELAMINATION BETWEEN THROUGH SILICON VIAS (TSVS) AND SILICON MATRIX PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION 2010, VOL 4, 2012, : 117 - 124
- [35] Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring 58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 847 - 852
- [36] Integrated Process for High Aspect Ratio Through Glass Vias 2017 18TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2017, : 1451 - 1454
- [40] An Experimental Verified Model for Cu Electrodeposition Simulation for the Filling of High Aspect Ratio Through Silicon Vias 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 2366 - 2370