Transistor Count Optimization of Conventional CMOS Full Adder & Optimization of Power and Delay of New Implementation of 18 Transistor Full Adder by Dual Threshold Node Design with Submicron Channel Length

A full adder circuit is one of the basic building blocks of a digital design. In general it is made by CMOS technology. In the CMOS technology the full adder is biult by 28 transistors. So, the transistor count is very high. The average power consumption, leakage power consumption and delay is very high. In this paper we made a new circuit which is made by mainly the Transmission Gate (TG) technology. In our circuit we use only 18 transistors to implement the Boolean Expression of the Full Adder. So, the transistor count decreases. Due to the decreasing of the transistor count we can reduces the average power, Leakage power, delay and noise. We also optimized our new circuit by different threshold of MOSFET technology.