共 32 条
[2]
BELLAOUAR A, 1995, LOW POER DIGITAL VLS
[3]
A REGULAR LAYOUT FOR PARALLEL ADDERS
[J].
IEEE TRANSACTIONS ON COMPUTERS,
1982, 31 (03)
:260-264
[7]
Choo I, 2001, IEEE SOUTHEASTCON 2001: ENGINEERING THE FUTURE, PROCEEDINGS, P196, DOI 10.1109/SECON.2001.923115
[8]
DAO H, 2001, P 35 AS C SIGN SYST, V2, P1322