Low temperature characterization of mobility in 14 nm FD-SOI CMOS devices under interface coupling conditions

被引:26
作者
Shin, Minju [1 ,3 ]
Shi, Ming [1 ]
Mouis, Mireille [1 ]
Cros, Antoine [2 ]
Josse, Emmanuel [2 ]
Kim, Gyu-Tae [3 ]
Ghibaudo, Gerard [1 ]
机构
[1] Minatec, IMEP LAHC, Grenoble INP, F-38016 Grenoble, France
[2] STMicroelectronics, F-38921 Crolles, France
[3] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea
基金
新加坡国家研究基金会;
关键词
UTBB FD-SOI; Low temperature characterization; Interface-coupling measurement; Electronics transport; CARRIER TRANSPORT; MOSFETS; ULTRATHIN;
D O I
10.1016/j.sse.2014.12.013
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, we demonstrate the powerful methodology of electronic transport characterization in highly scaled (down to 14 nm-node) FDSOI CMOS devices using cryogenic operation under interface coupling ineasurement condition. Thanks to this approach, the underlying scattering mechanisms were revealed in terms of their origin and diffusion center location. At first we study quantitatively transport behavior induced by the high-k/metal gate stack in long channel case, and then we investigate the transport properties evolution in highly scaled devices. Mobility degradation in short devices is shown to stem from additional scattering mechanisms, unlike long channel devices, which are attributed to process-induced defects near source and drain region. Especially in PMOS devices, channel-material related defects which could be denser close to front interface also induce mobility degradation. (C) 2014 Elsevier Ltd. All rights reserved.
引用
收藏
页码:30 / 35
页数:6
相关论文
共 20 条
[1]  
[Anonymous], INT ELECT DEV M
[2]   Carrier transport in HfO2/metal gate MOSFETs:: Physical insight into critical parameters [J].
Cassé, M ;
Thevenod, L ;
Guillaumot, B ;
Tosti, L ;
Martin, F ;
Mitard, J ;
Weber, O ;
Andrieu, F ;
Ernst, T ;
Reimbold, G ;
Billon, T ;
Mouis, M ;
Boulanger, F .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (04) :759-768
[3]   Bias-Engineered Mobility in Advanced FD-SOI MOSFETs [J].
Fernandez, Cristina ;
Rodriguez, Noel ;
Ohata, Akiko ;
Gamiz, Francisco ;
Andrieu, Francois ;
Fenouillet-Beranger, Claire ;
Faynot, Olivier ;
Cristoloveanu, Sorin .
IEEE ELECTRON DEVICE LETTERS, 2013, 34 (07) :840-842
[4]  
Grenouillet L, 2012, 2012 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), DOI 10.1109/IEDM.2012.6478974
[5]   CARRIER TRANSPORT NEAR THE SI/SIO2 INTERFACE OF A MOSFET [J].
HANSCH, W ;
VOGELSANG, T ;
KIRCHER, R ;
ORLOWSKI, M .
SOLID-STATE ELECTRONICS, 1989, 32 (10) :839-849
[6]  
Liu Q., 2013, 2013 IEEE INT EL
[7]  
Mouis M, 2010, NANOSCALE CMOS
[8]   Source/drain induced defects in advanced MOSFETs: what device electrical characterization tells [J].
Mouis, Mireille ;
Lee, Jae Woo ;
Jeon, Daeyoung ;
Shi, Ming ;
Shin, Minju ;
Ghibaudo, Gerard .
PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 11, NO 1, 2014, 11 (01) :138-145
[9]   High quality Germanium-On-Insulator wafers with excellent hole mobility [J].
Nguyen, Q. T. ;
Damlencourt, J. F. ;
Vincent, B. ;
Clavelier, L. ;
Morand, Y. ;
Gentil, P. ;
Cristoloveanu, S. .
SOLID-STATE ELECTRONICS, 2007, 51 (09) :1172-1179
[10]   Front- and back-channel mobility in ultrathin SOI-MOSFETs by front-gate split CV method [J].
Ohata, A. ;
Casse, M. ;
Cristoloveanu, S. .
SOLID-STATE ELECTRONICS, 2007, 51 (02) :245-251