Investigation of Band-Gap Engineered Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory with High-k Dielectrics in Tunnel Barrier and Its Impact on Charge Retention Dynamics

In this work, we intend to investigate the excellence of high-k dielectric materials for band-gap engineered Silicon-oxide-nitride-oxide-silicon (BE-SONOS) in tunnel layer for improving Program/Erase(P/E) speed and retention characteristics. In addition, we observed higher program speed of proposed material due to lower conduction band offsets. The proposed materials exhibit better erase speed along with improved retention. As a consequence, high-k tunnel oxide stacks possess good memory window with charge retained up to 94% (at room temperature) after a period of 10 years hence, overcomes program/ erase (P/E) speed and retention tradeoff as compared to the BE-SONOS with oxide/nitride/oxide (ONO) as tunneling stack. We found that while scaling gate length from 220 nm to 55 nm, the proposed material shows better retention as well as improved erase speed. Here, lower valence band and conduction band offsets and high permittivity of proposed materials results in better endurance for 1 K P/E cycles and improved tradeoff.