Low-temperature direct CVD oxides to thermal oxide wafer bonding in silicon layer transfer

被引：25

作者：

Tan, CS ^{[1
]}

Chen, KN ^{[1
]}

Fan, A ^{[1
]}

Reif, R ^{[1
]}

机构：

[1] MIT, Microsyst Technol Labs, Cambridge, MA 02139 USA

来源：

ELECTROCHEMICAL AND SOLID STATE LETTERS | 2005年 / 8卷 / 01期

关键词：

D O I：

10.1149/1.1825292

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

The bonding strength of low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition (PECVD) oxides to thermal oxide is studied. Prior to bonding, all CVD oxide wafers are subjected to careful surface preparation including densification, chemical-mechanical polishing, activation, and post-bond annealing to ensure high-quality bonding. All wafers show surface roughness and wafer bow suitable for bonding after the surface preparations. It is found that bonding strength increases upon annealing and saturates beyond 2 h of annealing for the temperature range of 200-300 degrees C. Tetraethyl orthosilicate source PECVD oxide is found to exhibit suitable bonding properties and can be used in applications such as silicon layer transfer. (C) 2004 The Electrochemical Society.

引用

页码：G1 / G4

页数：4

共 16 条

[1] 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration
Banerjee, K
Souri, SJ
Kapur, P
Saraswat, KC
[J]. PROCEEDINGS OF THE IEEE, 2001, 89 (05) : 602 - 633
[2] Morphology and bond strength of copper wafer bonding
Chen, KN
Tan, CS
Fan, A
Reif, R
[J]. ELECTROCHEMICAL AND SOLID STATE LETTERS, 2004, 7 (01) : G14 - G16
[3] The characteristic behavior of TMAH water solution for anisotropic etching on both silicon substrate and SiO2 layer
Chen, PH
Peng, HY
Hsieh, CM
Chyu, MK
[J]. SENSORS AND ACTUATORS A-PHYSICAL, 2001, 93 (02) : 132 - 137
[4] HAYASHI Y, 1990, S VLSI TECHN HON HI
[5] Fabricating capacitive micromachined ultrasonic transducers with wafer-bonding technology
Huang, YL
Ergun, AS
Hæggström, E
Badi, MH
Khuri-Yakub, BT
[J]. JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, 2003, 12 (02) : 128 - 137
[6] KEAST C, 2004, 3D TECHNOLOGY MODELI
[7] MALEVILLE C, 2000, INT SOI C WAK MA
[8] BONDING OF SILICON-WAFERS FOR SILICON-ON-INSULATOR
MASZARA, WP
GOETZ, G
CAVIGLIA, A
MCKITTERICK, JB
[J]. JOURNAL OF APPLIED PHYSICS, 1988, 64 (10) : 4943 - 4950
[9] PLUMMER JD, 2000, SILICON VLSI TECHNOL, P527
[10] REIF R, 2002, INT S QUAL EL DES SA

← 1 2 →