A 8.125-15.625 Gb/s SerDes Using a Sub-Sampling Ring-Oscillator Phase-Locked Loop

被引：0

作者：

Vamvakos, Socrates D. ^{[1
]}

Boecker, Charles ^{[1
]}

Groen, Eric ^{[1
]}

Wang, Alvin ^{[1
]}

Desai, Shaishav ^{[1
]}

Irwin, Scott ^{[1
]}

Rao, Vithal ^{[1
]}

Bottelli, Aldo ^{[1
]}

Chen, Jawji ^{[1
]}

Chen, Xiaole ^{[1
]}

Choudhary, Prashant ^{[1
]}

Hsieh, Kuo-Chiang ^{[1
]}

Jennings, Paul ^{[1
]}

Lin, Haidang ^{[1
]}

Pechiu, Dan ^{[1
]}

Rao, Chethan ^{[1
]}

Yeung, Jason ^{[1
]}

机构：

[1] MoSys Inc, Santa Clara, CA 95054 USA

来源：

2014 IEEE PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2014年

关键词：

Duty-cycle corrector; phase-locked loop; PLL; SerDes; sub-sampling PLL; voltage-mode transmitter; NOISE; CMOS; PLL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The paper describes a 8.125-15.625 Gbps medium-reach SerDes macro for use in a networking memory system. The SerDes employs a sub-sampling ring-oscillator phase-locked loop to obtain a large frequency range with low jitter performance. In addition, the transmitter uses a modified hybrid output driver and a multi-step duty-cycle corrector. The receiver uses a BER-based calibration loop to find the set of parameters that maximizes the receiver voltage margin. The transmitter output achieves 160fs RMS jitter and 10.9ps total jitter at 15.625 Gbps with 140fs duty-cycle distortion.

引用

页数：4

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