Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters

被引:25
作者
Chakrabarty, K [1 ]
Murray, BT
Iyengar, V
机构
[1] Duke Univ, Dept Elect & Comp Engn, Durham, NC 27708 USA
[2] Delphi Automot Syst, Saginaw, MI 48601 USA
基金
美国国家科学基金会;
关键词
built-in self-test (BIST); slow testers; test-per-clock BIST; test set embedding;
D O I
10.1109/92.894170
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
We present a new approach for built-in pattern generation based on the reseeding of twisted-ring counters (TRCs). The proposed technique embeds a precomputed deterministic test set for the circuit under test (CUT) in a short test sequence produced by a TRC. The TRC is designed using existing circuit flip-flops and does not add to hardware overhead beyond what is required for basic scan design. The test control logic is simple, uniform For all circuits, and can he shared among multiple CUTs. Furthermore, the proposed method requires no mapping logic between the test generator circuit and the CUT; hence it imposes no additional performance penalty. Experimental results for the ISCAS benchmark circuits show that it is indeed possible to embed the entire precomputed test set in a TRC sequence using only a small number of seeds.
引用
收藏
页码:633 / 636
页数:4
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