Analytical Modelling and Simulation of Si-Ge Hetero-Junction Dual Material Gate Vertical T-Shaped Tunnel FET

In this paper, a compact 2D analytical modelling of surface potential and simulation of Si-Ge hetero-junction Dual Material Gate Vertical t-shape T-FET is presented. In the proposed model, device is divided into two gate-metal work function named as tunneling gate and auxiliary gate. Both the biasing voltage of source and drain will have controlled effect on the device's surface potential which are used to access the depletion length of the tunneling junction. Therefore, the tunneling current will use the surface potential model as basic principle to drive the current model of the device. For solving the 2D Poisson equation with the necessary boundary conditions, parabolic approximation methods are employed. We test the reliability of surface potential on different parameters profile by varying it as a function of Si-Ge material mole-fraction, gate-source voltage, drain-source voltage, gate-oxide thickness, high k dielectric constant and different gate work function and various compound material used. Finally, we come out with the expression of the channel surface potential that will change in accordance with the drain and gate biasing voltage. The validity of the projected model has been confirm by showing agreement between the analytical findings and TCAD simulation results.