Fast Logic Optimization Using Decision Trees

被引:7
作者
de Abreu, Brunno A. [1 ]
Berndt, Augusto [2 ]
Campos, Isac S. [2 ]
Meinhardt, Cristina [2 ]
Carvalho, Jonata T. [2 ]
Grellert, Mateus [2 ]
Bampi, Sergio [1 ]
机构
[1] Univ Fed Rio Grande do Sul UFRGS, Inst Informat, PGMicro, Porto Alegre, RS, Brazil
[2] Univ Fed Santa Catarina UFSC, Dept Informat & Estat, PPGCC, Florianopolis, SC, Brazil
来源
2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年
关键词
Logic Synthesis; Logic Minimization; Machine Learning; Decision Trees;
D O I
10.1109/ISCAS51556.2021.9401664
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work evaluates the use of Decision Trees (DTs) methods for a fast logic minimization of Boolean functions. The proposed DT approach is compared to traditional Espresso logic minimizer and the minimization algorithms available in the ABC tool. The methods are compared with respect to the execution time, number of nodes and number of logic levels. The DT methods proved to be a faster alternative, reducing time by an average of 52% and 5.5% when compared to Espresso and ABC respectively, while keeping competitive results in terms of AIG depth and number of nodes. Additionally, in order to obtain smaller circuits at the cost of approximate results we tested DTs with limited tree depth. The trade-offs between synthesis time, circuit area and accuracy are also discussed. Compared to ABC, limiting the maximum tree depth leads to time savings of up to 52%, up to 86% less number of nodes, and up to 48% lower AIG depth, while maintaining acceptable accuracy results.
引用
收藏
页数:5
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