An effective built-in self-test for chargepump PLL

被引：2

作者：

Han, J ^{[1
]}

Song, D ^{[1
]}

Kim, H ^{[1
]}

Kim, YY ^{[1
]}

Kang, S ^{[1
]}

机构：

[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul 120749, South Korea

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2005年 / E88C卷 / 08期

关键词：

mixed-signal test; BIST; PLL;

D O I：

10.1093/ietele/e88-c.8.1731

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In order to provide an efficient test method for PLL which is a mixed-signal circuit widely used in most of SoCs, a novel BIST method is developed. The new BIST uses the change of phase differences generated by selectively alternating the feedback frequency. It provides an efficient structural test, reduces an area overhead and improves the test accessibility.

引用

页码：1731 / 1733

页数：3

共 8 条

[1] An all-digital DFT scheme for testing catastrophic faults in PLLs [J].

Azaïs, F ;

Bertrand, Y ;

Renovell, M ;

Ivanov, A ;

Tabatabaei, S .

IEEE DESIGN & TEST OF COMPUTERS, 2003, 20 (01) :60-67

[2] Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's [J].

Burbidge, MJ ;

Poullet, F ;

Tijou, J ;

Richardson, A .

ETW'02: 7TH IEEE EUROPEAN TEST WORKSHOP, PROCEEDINGS, 2002, :95-102

[3] Test evaluation and data on defect-oriented BIST architecture for high-speed PLL [J].

Kim, SW ;

Soma, M .

INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, :830-837

[4] An all-digital built-in self-test for high-speed phase-locked loops [J].

Kim, SW ;

Soma, M .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2001, 48 (02) :141-150

[5]

*MENT GRAPH CORP, 2001, GETT START ADV MS

[6] Challenges in analog and mixed-signal fault models [J].

Soma, M .

IEEE CIRCUITS AND DEVICES MAGAZINE, 1996, 12 (01) :16-19

[7]

Sunter S., 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), P532, DOI 10.1109/TEST.1999.805777

[8]

YAMAGUCHI T, 1999, P 5 IEEE INT MIX SIG, P263

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