A new fast and accurate method of extracting the parasitics of multi-layer packages

Due to the increase of the portable and high performance integrated circuit(IC) applications, package designs get smaller and more complex. Chip scaled multi-layer IC packages become one of the solutions to accommodate such requirements. In the design environment for the complicated packages, a fast and accurate interconnect parasitic extraction method is very important in order to explore alternative designs in a limited time and to cope with lacking of design margins. This paper proposes a novel interconnect parasitic extraction method which combines the advantages of the inherently fast two-dimensional(2-D) approach and accurate three-dimensional(3-D) approach. Thus, it efficiently models the 3-D effects around traces and vias such as the variable shaped reference plane and shielding, chip placement, package fringes, and current flows. The speed and the accuracy of parasitic extractions are substantially improved compared to the conventional method in the application of multi-layer packages for the leading edge memory products.