Minimization of mechanical and chemical strain at dielectric-semiconductor and internal dielectric interfaces in stacked gate dielectrics for advanced CMOS devices

This paper identifies fundamental aspects of Si-dielectric and internal dielectric interfaces that limit the ultimate performance of Si field effect transistor, FET, devices for scaled complementary metal oxide semiconductor, CMOS, integrated circuits. Three different interface limitations are discussed: i) residual suboxide bonding at Si-SiO2 interfaces, ii) bond induced mechanical strain at Si-Si3N4 and SiO2-Si3N4 interfaces, and iii) charged defects associated with heterovalent bonding at Si-high-k oxide and silicate dielectric interfaces.