40 Gbit/s/ch 2 x 2 switch IC using InP HEMTs

被引：1

作者：

Kamitsuna, H ^{[1
]}

Yamane, Y ^{[1
]}

Tokumitsu, M ^{[1
]}

Sugahara, H ^{[1
]}

Muraguchi, A ^{[1
]}

机构：

[1] NTT Corp, NTT Photon Labs, Atsugi, Kanagawa 2430198, Japan

来源：

ELECTRONICS LETTERS | 2005年 / 41卷 / 09期

关键词：

Integrated circuits;

D O I：

10.1049/el:20050261

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power 2 x 2 switch IC using InP HEMTs as cold FETs is presented. It has a logic-level-independent interface since no signal line is grounded. The IC yields low insertion loss of 1.5-2.7 dB and high isolation of > 21.2 dB below 30 GHz. When two 40 Gbit/s signals were input, error-free operation was confirmed with virtually zero power dissipation.

引用

页码：532 / 534

页数：3

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