An Empirical Network-on-Chip Topology Design for Multicore Architectures

Network-on-chip is very important part of the current and way forward for computer architecture. It is mainly used in multiprocessor System-on-Chips and in Chip Multiprocessing. The number of cores in multicore processors are consistently increasing to build the processor in rapid and reliable way. The quantity of processing assets in System-on-Chips have been steadily expanding to meet better computational requirements. With the help of Network-on-Chips the back-end wiring involved has radically reduced in System-on-Chip. But the power, time, bandwidth required grows rapidly across the innovation ages. To overcome such challenges of present System-on-Chip, Network-on-Chip technology is invented. This work gives a design of a topology for Network-on-Chip based system to provide better performance in terms of throughput, latency, area and energy. The system is modeled in gem5 simulator using garnet interconnection networks. splash2 benchmark suit is used for trace driven simulations. Drawing on insights from the results, the proposed topology provides 12% improvement in throughput, 52% improvement in area and 33% improvement in latency over the fat tree topology.