An accurate process model has always been the key for successful implementation of model-based Optical Proximity Correction (OPC). As CD control requirements become severe at the 45nm and 32nm device generations, process model accuracy requirements become more stringent. In previous generations, certain systematic process and tool fingerprints could be safely ignored. For example, lens apodization and mask pellicle film induced transmission loss, lens vectorial fingerprint(i.e. Jones pupil), illuminator polarization profile, and etc were ignored in conventional OPC modeling approaches., These effects are now playing a more important role in OPC modeling as technology scales down. Using conventional OPC model may lead to under-correction of the design layout during OPC, and this will result in large number of post-OPC layout hot spots which have patterning issues when the OPCed layout is exposed on the scanner. We designed an OPC correction and verification flow which can efficiently capture the post-OPC layout hot spots due to under-correction using traditional OPC model, and this flow further fixes these detected hot spots. Our simulations demonstrated that this proposed flow is able to achieve an OPC perforrnance of 2.25nm CD error range and 0.26nm CD error standard deviation on poly gate layer for 45nm SRAM design. And this validated the efficiency of the proposed flow.
