The design and implementation of reconfigurable multiplier with high flexibility

被引：0

作者：

Shi, Jiangyi ^{[1
]}

Jing, Gang ^{[1
]}

Di, Zhixiong ^{[1
]}

Yang, Si ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Minist Educ, Key Lab Wide Band Gap Semicond Mat & Devices, Xian 710071, Peoples R China

来源：

2011 INTERNATIONAL CONFERENCE ON ELECTRONICS, COMMUNICATIONS AND CONTROL (ICECC) | 2011年

关键词：

multiplier; reconfigurable; DSP; MAC; FPGA;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a reconfigurable mechanism for the multiplier. The proposed mechanism is applied to generate a multiplier, whose data width, type and pipeline depth can be customized. The data width of each operand of these generated multipliers can be configured for 4i where i=1, 2, 3, 4, 5, 6, 7, 8. And the data type of operand can be unsigned or signed at will. The multiplier is composed of the smallest multiplier-cells, the 4-bit multiplier. Synthesized results could reach as high as 425.53MHz using SMIC 0.13um CMOS technology library under the worst case condition.

引用

页码：1095 / 1098

页数：4