Self-checking of FPGA-based control units

被引：16

作者：

Levin, I ^{[1
]}

Sinelnikov, V ^{[1
]}

机构：

[1] Tel Aviv Univ, Ctr Technol Educ, Dept Comp Sci, IL-58102 Holon, Israel

来源：

NINTH GREAT LAKES SYMPOSIUM ON VLSI, PROCEEDINGS | 1999年

关键词：

D O I：

10.1109/GLSV.1999.757436

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper introduces a new technique for on-line checking of FPGA based Control Units CUs). This technique is based on the architecture,. comprising two portions: a self-checking CL; and a separate totally self-checking (TSC) checker, Each of these portions is implemented as a combination of an Evolution block and an Execution block Comparison of code vectors being transferred between the blocks of the portions enables providing a totally self-checking property: The self-checking CU is implemented in a form of one-rail network of interconnected pre-designed LCT-based configurable logical blocks. The self-checking checker is a Sum-Of-Minterms based checker. The proposed technique: a) does not require any encoding of output words: b) uses one-rail design, thereby drastically decreasing the required overhead.

引用

页码：292 / 295

页数：4