A Low-Power High-Linearity Symmetrical Readout Circuit for Capacitive Sensors

This paper presents a symmetrical readout circuit for capacitive sensors. Based on charge transfer principle, it is insensitive to stray capacitors. Introducing a reference branch, this symmetrical readout circuit can enlarge its linear range, reduce amplifier offsets and reject common-mode noise and even-order distortions. Chopper stabilization technique is used to reduce the negative effects of the amplifier offset and flicker (1/f) noise. A Verilog-A based varactor is used to model the real variable sensing capacitor. Simulation results are given for sensing capacitor changing frequency at 1 KHz. Metal-Insulator -Metal (MIM) capacitor array is designed on chip for measurement. Measurement results show that this circuit can achieve sensitivity of 370 mV/pF, linearity error below 1 % and power consumption as low as 2.5 mW. This symmetrical readout circuit can respond to FPGA controlled sensing capacitor array changed every 1 ms.