Patterned electrode vertical field effect transistor: Theory and experiment

被引:69
作者
Ben-Sasson, Ariel J. [1 ]
Tessler, Nir [1 ]
机构
[1] Technion Israel Inst Technol, Dept Elect Engn, Sarah & Moshe Zisapel Nanoelect Ctr, IL-3200 Haifa, Israel
基金
以色列科学基金会;
关键词
THIN-FILM TRANSISTORS; VOLTAGE; SEMICONDUCTORS; PERFORMANCE; CHANNEL;
D O I
10.1063/1.3622291
中图分类号
O59 [应用物理学];
学科分类号
摘要
We present a theoretical and experimental investigation of the recently reported new architecture of a patterned electrode vertical field effect transistor (PE-VFET). The investigation focuses on the role of the embedded source electrode architecture in the device behavior. Current-voltage characteristics was unraveled through the use of a self-consistent numerical simulation resulting in guidelines for the PE-VFET architecture regarding the On/Off current ratio, output current density, and apparent threshold voltage. Current modulation characteristics are obtained through the formation of virtual contacts at the PE nano-features (i.e., perforations) under gate bias, which lead to the formation of vertical channels under drain bias. As the vertical channel is formed the device characteristics change from contact-limited to space-charge-limited. The analytical model strength is shown with the parameter extraction procedure applied to a measured PE-VFET device fabricated using block copolymer lithography and with the appropriate simulation results. (C) 2011 American Institute of Physics. [doi:10.1063/1.3622291]
引用
收藏
页数:12
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