A Hardware-In-Loop Platform for Three-Phase Grid-Tied PV Array Fed Multilevel Converter

被引：2

作者：

Yadav, Shivam Kumar ^{[1
]}

Mishra, Nidhi ^{[1
]}

Singh, Bhim ^{[1
]}

Chandra, Ambrish ^{[2
]}

Al-Haddad, Kamal ^{[2
]}

机构：

[1] Indian Inst Technol Delhi, Dept Elect Engn, New Delhi 110016, India

[2] ETS, Dept Elect Engn, 1100 Rue Notre Dame Ouest, Montreal, PQ H3C 1K3, Canada

来源：

2019 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE (ITEC-INDIA) | 2019年

关键词：

Hardware-In-Loop; Multilevel Converters; Power Quality; Solar Photovoltaic Array;

D O I：

10.1109/ITEC-India48457.2019.ITECINDIA2019-233

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper deals with a photovoltaic (PV) array fed three-phase seven-level converter grid-tied configuration. The proposed system integrates PV array side to AC grid using minimum DC sources and single-phase transformers. The decoupled controller of the system exhibits active and reactive current controllers with coupling compensation network. A low-frequency switching is implemented using carrier-based pulse width modulation (PWM) technique. The system inherits the advantages of simple controller, single DC source and galvanic isolation. A model of the system is developed and its behavior is simulated in MATLAB/Simulink and validated in real-time using hardware in loop (HIL) platform using OPAL-RT.

引用

页数：5

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