Study of the SOI LDMOS With Low Conduction Loss and Less Gate Charge

This brief focuses on the silicon-on-insulator (SOI) split gate (SG) superjunction (SJ) lateral double-diffused MOSFET (LDMOS), in which the p-column is not only utilized to compensate the fields produced by the opposite charges in the drift region, but also further acting as an SG. The accumulation layers of an electron are formed in the drift region during the on-state, providing the lower resistance paths for electric current, which leads to a decrease in the specific on-resistance (R-ON,R- sp). Furthermore, because of the semiconductor-insulator-semiconductor (SIS) capacitor, not all of the positive charges in the n-drift region intend to induce the negative charges on the gate, since there is a Miller capacitance, and thus the gate charge (Q(G)) is reduced with the weakened Miller effect. The simulation results indicate that comparing with the previous SOI SJ-LDMOS, R-ON,R- sp and QG can be reduced by 35% and 17%, respectively, leading to a 46% improvement of figure of merit for the proposed structure.