An algorithm for the ηT pairing calculation in characteristic three and its hardware implementation

被引：18

作者：

Beuchat, Jean-Luc ^{[1
]}

Shirase, Masaaki ^{[2
]}

Takagi, Tsuyoshi ^{[2
]}

Okamoto, Eiji ^{[1
]}

机构：

[1] Univ Tsukuba, Tsukuba, Ibaraki 305, Japan

[2] Future Univ Hakodate, Hakodate, Hokkaido, Japan

来源：

18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/ARITH.2007.10

中图分类号：

O29 [应用数学];

学科分类号：

070104 ;

摘要：

In this paper, we propose a modified eta T pairing algorithm in characteristic three which does not need any cube root extraction. We also discuss its implementation on a low cost platform which hosts an Altera Cyclone II FPGA device. Our pairing accelerator is ten times faster than previous known FPGA implementations in characteristic three.

引用

页码：97 / +

页数：3

共 50 条

[31] Hirschberg's algorithm on a GCA and its parallel hardware implementation [J].

Jendrsczok, Johannes ;

Hoffmann, Rolf ;

Keller, Joerg .

EURO-PAR 2007 PARALLEL PROCESSING, PROCEEDINGS, 2007, 4641 :815-+

[32] A Modified Spiral Search Algorithm and its Embedded Hardware Implementation [J].

Kroupis, Nikolaos ;

Dasygenis, Minas ;

Soudris, Dimitrios ;

Thanailakis, Antonios .

PROCEEDINGS OF WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY, VOL 7, 2005, 7 :375-378

[33] A PCA Acceleration Algorithm For WiFi Sensing And Its Hardware Implementation [J].

Wang, He ;

Wang, Qitong ;

Huang, Leilei ;

Shi, Chunqi ;

Zhang, Runxi .

2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,

[34] Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation [J].

Alaparthi, Srikanth ;

Gulati, Kanupriya ;

Khatri, Sunil P. .

ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, :2225-2228

[35] A parametric hardware fine acceleration/deceleration algorithm and its implementation [J].

Ji, Shuai ;

Hu, Tianliang ;

Zhang, Chengrui ;

Sun, Shuren .

INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY, 2012, 63 (9-12) :1109-1115

[36] An Improved Montgomery Modular Multiplication Algorithm and Its Hardware Implementation [J].

Ren S. ;

Wang H. ;

Hao Y. ;

Xue C. .

Beijing Ligong Daxue Xuebao/Transaction of Beijing Institute of Technology, 2024, 44 (03) :306-311

[37] A modified spiral search algorithm and its embedded hardware implementation [J].

Kroupis, N ;

Dasygenis, M ;

Soudris, D ;

Thanailakis, A .

ENFORMATIKA, VOL 7: IEC 2005 PROCEEDINGS, 2005, :375-378

[38] Hardware implementation for a genetic algorithm [J].

Chen, Pei-Yin ;

Chen, Ren-Der ;

Chang, Yu-Pin ;

Shieh, Leang-San ;

Malki, Heidar A. .

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2008, 57 (04) :699-705

[39] A HARDWARE IMPLEMENTATION OF AN AUTOREGRESSIVE ALGORITHM [J].

SMITH, MR ;

SMIT, TJ ;

NICHOLS, SW ;

NICHOLS, ST ;

ORBAY, H ;

CAMPBELL, K .

MEASUREMENT SCIENCE AND TECHNOLOGY, 1990, 1 (10) :1000-1006

[40] Efficient Architecture for the Tate Pairing in Characteristic Three [J].

Li, Qingwei ;

Wang, Zhongfeng ;

Zhang, Xinmiao ;

Liu, Xingcheng .

2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, :1111-+

← 1 2 3 4 5 →