An algorithm for the ηT pairing calculation in characteristic three and its hardware implementation

被引:18
|
作者
Beuchat, Jean-Luc [1 ]
Shirase, Masaaki [2 ]
Takagi, Tsuyoshi [2 ]
Okamoto, Eiji [1 ]
机构
[1] Univ Tsukuba, Tsukuba, Ibaraki 305, Japan
[2] Future Univ Hakodate, Hakodate, Hokkaido, Japan
来源
18TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS | 2007年
关键词
D O I
10.1109/ARITH.2007.10
中图分类号
O29 [应用数学];
学科分类号
070104 ;
摘要
In this paper, we propose a modified eta T pairing algorithm in characteristic three which does not need any cube root extraction. We also discuss its implementation on a low cost platform which hosts an Altera Cyclone II FPGA device. Our pairing accelerator is ten times faster than previous known FPGA implementations in characteristic three.
引用
收藏
页码:97 / +
页数:3
相关论文
共 50 条
  • [1] Efficient hardware for the Tate pairing calculation in characteristic three
    Kerins, T
    Marnane, WP
    Popovici, EM
    Barreto, PSLM
    CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, 2005, 3659 : 412 - 426
  • [2] Efficient Hardware Architecture of ηT Pairing Accelerator Over Characteristic Three
    Chung, Szu-Chi
    Wu, Jing-Yu
    Fu, Hsing-Ping
    Lee, Jen-Wei
    Chang, Hsie-Chia
    Lee, Chen-Yi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (01) : 88 - 97
  • [3] Hardware acceleration of the Tate pairing in characteristic three
    Grabher, P
    Page, D
    CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, 2005, 3659 : 398 - 411
  • [4] Improved algorithm of the Tate pairing in characteristic three
    Wu, Ting
    Du, Huan-Qiang
    Zhang, Min
    Wang, Rong-Bo
    PROCEEDINGS OF THE FIRST INTERNATIONAL SYMPOSIUM ON DATA, PRIVACY, AND E-COMMERCE, 2007, : 453 - 455
  • [5] Hardware implementation of finite fields of characteristic three
    Page, D
    Smart, NP
    CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2002, 2002, 2523 : 529 - 539
  • [6] An efficient algorithm for modulus operation and its hardware implementation in prime number calculation
    Wijesinghe, W. A. Susantha
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2025, 191
  • [7] FPGA and ASIC implementations of the ηT pairing in characteristic three
    Beuchat, Jean-Luc
    Doi, Hiroshi
    Fujita, Kaoru
    Inomata, Atsuo
    Ith, Piseth
    Kanaoka, Akira
    Katouno, Masayoshi
    Mambo, Masahiro
    Okamoto, Eiji
    Okamoto, Takeshi
    Shiga, Takaaki
    Shirase, Masaaki
    Soga, Ryuji
    Takagi, Tsuyoshi
    Vithanage, Ananda
    Yamamoto, Hiroyasu
    COMPUTERS & ELECTRICAL ENGINEERING, 2010, 36 (01) : 73 - 87
  • [8] ADAPTIVE THRESHOLDING ALGORITHM AND ITS HARDWARE IMPLEMENTATION
    YANG, JD
    CHEN, YS
    HSU, WH
    PATTERN RECOGNITION LETTERS, 1994, 15 (02) : 141 - 150
  • [9] Algorithms and arithmetic operators for computing the ηT pairing in characteristic three
    Beuchat, Jean-Luc
    Brisebarre, Nicolas
    Detrey, Jeremie
    Okamoto, Eiji
    Shirase, Masaaki
    Takagi, Tsuyoshi
    IEEE TRANSACTIONS ON COMPUTERS, 2008, 57 (11) : 1454 - 1468
  • [10] Hardware and software normal basis arithmetic for pairing-based cryptography in characteristic three
    Granger, R
    Page, D
    Stam, M
    IEEE TRANSACTIONS ON COMPUTERS, 2005, 54 (07) : 852 - 860