Modeling and Understanding of External Latchup in CMOS Technologies-Part I: Modeling Latchup Trigger Current

被引：19

作者：

Farbiz, Farzan ^{[1
,2
]}

Rosenbaum, Elyse ^{[1
,2
]}

机构：

[1] Univ Illinois, Dept Elect & Comp Engn, Urbana, IL 61801 USA

[2] Univ Illinois, Coordinate Sci Lab, Urbana, IL 61801 USA

来源：

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | 2011年 / 11卷 / 03期

关键词：

Circuit models; guard rings (GRs); latchup;

D O I：

10.1109/TDMR.2011.2159504

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper elucidates the roles of substrate majority and minority carriers in triggering external latchup, where the term external signifies that the substrate current injection occurs at a location away from the p-n-p-n structure. Circuit-level models are presented that allow one to identify the worst case testing condition and to simulate the value of the latchup trigger current. The model captures the effect of guard rings. The simulation results are compared to measurement results, and good agreement is observed, for a variety of CMOS technologies.

引用

页码：417 / 425

页数：9